nova.gay - risk-III

logic gates - the building blocks of the hardware

in this chapter i am introducing you to
the ternary logic gates provided by The Ternary Manifesto - Douglas W. Jones
//note: i will only go over the gates that are new and arent just ternary //implenetations of their binary counterparts //note: other implementations of ternary logic gates exist,
//however they will be of no importance to us

here you can get a quick peek of every logic gate we have to out disposal

why are there a dip switches?
well the answer to that is easy,
as the currently used simulator (logism evolution) doesnt natively support ternary,
we have to come up with a different way to represent the -, 0, and +
we will be doing that by having bit 0 (dipswitch 1) represent +
bit 1 (dipswitch 2) represents -
and no dipswitch flipped being 0

in our ternary simmulation it is theoretically possible for both - and +
to be activated at the same time,
this results in our design breaking,
however this will never happen until we set it like that
on purpose

going closer into the gates themselves

equal
the equal gates have a single function;
to check if input fullfils a specific condition
if it does the result will be +
if it does not the result will be -

so, what do these gates do?
simple, if input (in this case - as switch 2 is being activated)
equals the value written on the gate the output will be +
otherwise the output will be -

this being said,
if the input is -,
the output in =0 will be - (blue)
the output in =+ will be - (blue)
the output in =- will be + (red)

there also exist a = gate wich just compares two inputs
the results follow the same pattern the above given =x gates do

[picture of increment and decrement gates]

the increment(+1) and decrement(-1) gates,
akin to shift shift logic in binary
move the value of the input either one up
or one down

if the input is 0,
the output will either be increased (+)
or decreased (-)

should the input be +, the output at the +1 will overflow and become -,
the output at the -1 will decrease and become 0

while the modulo 3 sum gate doesnt necessarily need a dedicated gate
as it can be constructed using already existing gates,
i have implemented it for the exact same reason why i have implemented
the amax(ternary equivalent to to the nor gate) gate and
the amin(ternary equivalent to the nand gate) gate as seperate gates,
to make it easier to use them and have myself not reconstruct them manually
every time i want to use them

i dont have anything more to say about the sum gate but to give you the truth table
[======] | input
[======] | - 0 +
----------------
[====] - | + - 0
output 0 | - 0 +
[====] + | 0 + -

the consensus gate is a different = gate in where the output is
what the input is so long both inputs are equal,
otherwise the output is 0

just like the sum gate it can be implemented using already existing gates
[======] | input
[======] | - 0 +
----------------
[====] - | - 0 0
output 0 | 0 0 0
[====] + | 0 0 +

the accept anything gate is a variation of the consensus gate
in where only one input has to be set to get its output whith
0 only appearing should both inputs be 0,
or both inputs dissagreeing,
being where one input is + and the other one -

just like in the case of the sum gate, i have nothing more to say
[======] | input
[======] | - 0 +
----------------
[====] - | - - 0
output 0 | - 0 +
[====] + | 0 + +

with all gates now avalable,
we can move on to the next step,
memory management

in the next chapter i will make a basic memory cell
designed for ternary data storage
and will use said memory cell to make a register

more about the gates
check out the .circ on gittea

chapter 1 - gates