memory - because mine is bad
in this chapter i am going to design a register
//a multi value logic (everything other than binary)
//flip flop is called a flip flap flop (fff)
//with some calling it a flip flop flap
//note: as our simulator logisim evolution is a binary logic simulator
//there are some weird quirks we have to account for
![[picture of a 27trit register]](media/ch2_27trit_reg.png)
a 27 trit register can hold 7,625,597,484,987 different values
//177,547.277% of the 32 bit int
![[picture of a single memory cell]](media/ch2_memory_cell.png)
here we can see a single memory cell
in here we can see the input being - on the bottom input
//in this case switch 1 is active,
//rather than switch 2
//seen in the wire merger as bit 1 is active
the truth table for the memory cell is the following
a b output
----------
x 0 keep saved value
x + save value a
x - output saved value
![[picture of the insides of the memory cell]](media/ch2_fff.png)
here we can see the internals of the memory cell
the most important part of the memory cell is the amin fff
which works is just a ternary nand flip flop
and works just as youd expect it would
however what is interesting is the load and save aspect
of the module
as our simulator is binary having a 0 in our fff
would result our design to oscillate
//fall into an endless loop and break
which is suboptimal as we wouldnt be able to change
the value inside the simulator anymore
this oscillation is easily midigated by simply not having it go 0
so we are going to use - to make our fff keep
and use + to save
so unless our input on b is +,
it will keep the fff where it is with the =+ gate as the input will be -
with that we can now add the ability to load our saved value
using a down clamp
//a min gate with a constant 0
clamping down will result our input to output - when the input is -
otherwise the output is 0
//this is just a =- gate where the output on false is 0
the xor at the output will output - when both inputs are equal
and + when both inputs are not equal
unless one or both inputs are 0,
in which the output will be 0
![[picture of the memory cells oscillating]](media/ch2_oscillation.png)
why does it still oscillate?
simply said because we just started our simulation no signal was computed
and thus the output at the =+ gate hasnt initialized to - yet
therefore we just need to save anything once to fix this
//this will be done during the power on process of our cpu
//we dont have to worry about it,
//however we should keep that in mind that this happens
with memory now working we can concentrate on the risc part of this project
next chapter we will create risc-v fork which tries to both
follow how ternary benifits cpu design and follow the risc-v standard
//thats where the name risc-III comes from
//or should i call this risc-v.3?
check out the .circ on gittea